每天进步一点点------基础实验_13_有限状态机 ：Mealy型序列检测器

 /*********************************************************************************
 * Company                    :
 * Engineer                    : 空气微凉
 *
 * Create Date                : 00:00:00 22/03/2013
 * Design Name                :
 * Module Name                :
 * Project Name                :
 * Target Devices            :
 * Tool versions            :
 * Description                :
 *                       http://www.cnblogs.com/kongqiweiliang/
 * Dependencies                :
 *
 * Revision                    :
 * Revision                    : 0.01 - File Created
 * Additional Comments    : 基础实验_13_有限状态机 ：Mealy型序列检测器
 ********************************************************************************/
 `timescale 1ns/1ps
 `define    UD  #
 /*******************************************************************************/
 module SEQ_REC_MEALY
 (
     //system interface
     input                                     iCLK_50        ,//50MHz
     input                                     iRESET         ,//system interface
     //Interface package
     input                                     iDAT_EN        ,//
     input                                     iDAT            ,//
     output                                oDAT             //
 );
 //-------------------------------------------------------------------------------
 parameter   FSM_IDLE    =    'h0;
 parameter   FSM_0        =    'h1;
 parameter   FSM_1        =    'h2;
 parameter   FSM_2        =    'h3;

 reg  [:]  FSM_CS;
 reg  [:]  FSM_NS;

 always@(posedge iCLK_50 or negedge iRESET)begin
     if(!iRESET)
         FSM_CS <= FSM_IDLE;
     else
         FSM_CS <= FSM_NS;
 end
 always@(*)begin
     case(FSM_CS)
         FSM_IDLE    :
                         if(iDAT_EN && iDAT)                FSM_NS = FSM_1;
                         else if(iDAT_EN && (!iDAT))      FSM_NS = FSM_0;
                         else                                  FSM_NS = FSM_IDLE;
         FSM_0        :
                         if(!iDAT)                              FSM_NS = FSM_0;
                         else if(iDAT)                         FSM_NS = FSM_1;
                         else                                  FSM_NS = FSM_IDLE;
         FSM_1        :
                         if(!iDAT)                              FSM_NS = FSM_0;
                         else if(iDAT)                         FSM_NS = FSM_2;
                         else                                  FSM_NS = FSM_IDLE;
         FSM_2        :
                         if(!iDAT)                              FSM_NS = FSM_0;
                         else if(iDAT)                         FSM_NS = FSM_2;
                         else                                  FSM_NS = FSM_IDLE;
         default  :
                          FSM_NS = FSM_IDLE;
     endcase
 end

 assign oDAT = ((FSM_CS == FSM_2) && iDAT) ? 'h1 : 1'h0;
 //-------------------------------------------------------------------------------
 endmodule