HDLBits->Verilog Language->Modules:Hierarchy->Modules and vectors

题目要求如上不再赘述，主要关注到最后的四选一多路选择器。

最初编写的选择器代码如下

always@(sel)
        case(sel)
            2'd0:q <= d;
            2'd1:q <= in1;
            2'd2:q <= in2;
            2'd3:q <= in3;
            default: ;

此时会爆出警告

Warning (10235): Verilog HDL Always Construct warning at top_module.v(27): variable "d" is read inside the Always Construct but isn't in the Always Construct's Event Control File: /home/h/work/hdlbits.4515504/top_module.v Line: 27

Warning (10235): Verilog HDL Always Construct warning at top_module.v(28): variable "in1" is read inside the Always Construct but isn't in the Always Construct's Event Control File: /home/h/work/hdlbits.4515504/top_module.v Line: 28

Warning (10235): Verilog HDL Always Construct warning at top_module.v(29): variable "in2" is read inside the Always Construct but isn't in the Always Construct's Event Control File: /home/h/work/hdlbits.4515504/top_module.v Line: 29

然后修改代码为

always@(sel,d,in1,in2,in3)
        case(sel)
            2'd0:q <= d;
            2'd1:q <= in1;
            2'd2:q <= in2;
            2'd3:q <= in3;
            default: ;
        endcase

此时警告消失，这是因为在always组合逻辑电路中，敏感列表应当包含always块中所有的输入信号才不会引发错误，当然此处也可以用

always@(*)
        case(sel)
            2'd0:q <= d;
            2'd1:q <= in1;
            2'd2:q <= in2;
            2'd3:q <= in3;
            default: ;
        endcase

这样才能保证每一个敏感信号都是能够正常起作用的。