(转) 使用vivado创建工程 2

Build the hardware platform and export to SDK

A basic ARM hardware platform is now configured. The configuration includes clock and DDR controller settings. It also enabled and maps a UART peripheral. Now we will build the hardware platform and export to the Software Development Kit (SDK) so that an application can be developed.

1. Since we have added an IP in the design we need to generate the HDL files that are required for implementation, simulation and synthesis. In this first design we only use PS and there is nothing designed in the PL but we still need to do this step in order to hook up the design to the top level. Expand <Design Sources> in the Sources pane, right click system(system.bd) and select <Generate Output Products>. This window pops-up. Click Generate to start the generation.

2. Even though the whole design is made in IP integrator we still need a top level HDL in order to  identify the top of the design. The only thing needed is a top level HDL wrapper that instantiates the Block Design and it can be created automatically by right-clicking system(system.bd) and selecting <Create HDL Wrapper).

3. Click OK to let Vivado generate the system_wrapper.v top-level module for the design.

4. Notice that the embedded system (system.bd) is now a sub-module of system_wrapper.

5. We now have a design that can be used to configure the ZedBoard. But first we have to export the design to Vivado SDK where we will write the c-program that will run in the ARM processing system. In Vivado menu select File->Export->Export Hardware for SDK...

6. The Vivado design tool exports the Hardware Platform Specification for our design (system.xml) to SDK. In addition to system.xml, there are four more files exported to SDK. They are ps7_init.c, ps7_init.h, ps7_init.tcl, and ps7_init.html. The system.xml file opens by default when SDK launches. The address map of our system read from this file is shown in the SDK window.

The ps7_init.c and ps7_init.h files contain the initialization code for the Zynq processing system and initialization settings for DDR, clocks, plls and MIOs. SDK uses these settings when initializing the processing system so that the applications can be run on top of the processing system.

Here are some of the files generated during the hardware design session. No it is time to start writing some software. We will start with the simplest program called "Hello World".

In Vivado 2015.1 the file structure looks like this: